Forum: Geek Forum
Topic: The Hammer will 0wn us all.
started by: damien_s_lucifer
Posted by damien_s_lucifer on Oct. 16 2001,03:17
< I saw. I read. I came. >
Posted by CatKnight on Oct. 16 2001,04:01
i have no idea what any of that means but it looks cool
Posted by MattimeoZ80 on Oct. 16 2001,04:09
i know a guy that would die for intel. anytime i say amd is better he has to try to one-up me, ands like "intel will always be better than every amd regardless" and he dismisses sites like anandtech and tomshardware and hardocp as "opinionated non-professional websites". he refuses to believe the benchmarks, i'm just like "wtf". amd 0wns j00... i personally think he just doesn't want to admit that my comp is better -- and less expensive.
Posted by ASCIIMan on Oct. 16 2001,07:23
Umm... yeah. I almost went back to Intel because of a flakey Via chipset. Then I got a new MB with an AMD 760 chipset and it was all better.

Surely an xHammer wiLL r0x0r my b0x0r next time I upgrade. Mmmmm... Glueless SMP, integrated memory controllers, and an integrated northbridge (oh yeah, and 64 bits are nice too).

Posted by miNus on Oct. 16 2001,10:32
Don't forget HyperTransport. It will 0wn j00!

Pages 29-37 are particularly nice.

Posted by Dark Knight Bob on Oct. 16 2001,10:55
mmm confusing techy words

------------------
simultaneity is not absolute. So just because you think i'm wrong, from my frame of reference i'm right!

Posted by damien_s_lucifer on Oct. 16 2001,17:53
quote:
Originally posted by MattimeoZ80:
i know a guy that would die for intel

I've met plenty of those. My roommate used to be one until he noticed my machine is rock solid and his crashes all the time.

I know it's his piece of shit power supply that's doing it, but if he wants to buy AMD, who am I to discourage him?

Posted by damien_s_lucifer on Oct. 16 2001,18:06
12 stage fetch/exec pipeline... mmm...

For those who don't understand the fuss about the # of pipeline stages, as a general rule :

fewer # of pipeline stages = higher average instructions per cycle (IPC)

The reason this happens is because of execution branches. Instruction execution happens near the end of a CPU's pipeline. When the CPU is executing instructions that are sequential, it can keep one instruction in every stage of the pipeline. Every clock cycle causes one or more instructions to execute, and everything in the pipeline gets shifted forward.

When a branch happens, though, the CPU has to discard everything in the pipeline and start anew. This means the CPU stalls for as many cycles as the pipeline is long - no instructions execute until the pipeline is full again.

The CPU *tries* to predict ahead of time where a program will go next to prevent these stalls. If you're lucky, the CPU guesses correctly, and a branch DOESN'T stall the CPU. But branch prediction can only do so much. In a normal environment EVERY CPU stalls thousands or even millions of times a second.

On the other hand, having more stages in the pipeline means that each stage has to do less work, which means you can crank the clock speed higher than you could otherwise.

I believe the Athlon has a 9-stage vs. 20 for the P4. This is one of the main reasons the P4 is a slug - even though it's execution engine runs at 2X clock speed, every mispredicted branch causes a minimum 20-cycle stall, vs. only 9 cycles on the Athlon (and 12 on the Hammer).

So it looks like the Hammer will almost certainly be about the same speed as the Athlon - probably a tad slower at integer ops, and a tad faster at FP. It will definatley be a hell of a lot faster than the P4, clock for clock.

Posted by miNus on Oct. 16 2001,21:57
quote:
damien_s_lucifer stated the following obvious shit:
[Hammer] will definatley be a hell of a lot faster than the P4, clock for clock.

Well, duh!

I mean, if the Athlon is faster than the P4 clock for clock, you'd hope the Hammer damn well better be!

Posted by damien_s_lucifer on Oct. 16 2001,22:08
I doubt the Hammer will be as fast as the Athlon clock-for-clock, though. But it should be able to hit higher clock speeds, and it will be a moot point when running native 64-bit apps. 64-bit processing r0x0rs.
Posted by miNus on Oct. 16 2001,22:36
So does up to 8 processors and up to 8 DDR Dimms for EACH processor (only 128 GB total RAM )

Heh, damn. I guess I'm going to have to start stocking up with Crucial

Posted by ASCIIMan on Oct. 16 2001,23:49
Or Muskkin... Because Mushkin 0wnZ J00 and J00R B0X0RZ.
Posted by CaptainEO on Oct. 18 2001,03:34
Yeah I think the Hammer architecture is definitely a better fit for today's environment than IA-64. AMD was genius to add 64-bit addressing as just an incremental improvment to the x86 architecture - this way we can retarget all of our current software and compiler technology to Hammer with minimal effort. IA64, while a really nice and clean design, is just too *different* from x86. It's going to take years before we have compilers that generate decent IA64 code. Plus all of our investment in writing optimized code for x86 just goes out the window.

Sure, x86 has a pretty dumb instruction set, but these days what goes on inside the CPU is almost irrelevant compared to memory bandwidth and cache issues. It does no good to have a clean, optimal CPU architecture when it's hooked up to a mediocre memory system. (SPARC, PowerPC, etc)

Posted by The_Stomper on Oct. 18 2001,03:55
The Hammer will never 0wn me. For I will 0wn a Hammer (or two )

"Hello, Intel. Who's j00 daddy? That's right. Yes I am."

Posted by miNus on Oct. 18 2001,11:38
No. The Hammer would legally win custody over you.

Now, in order to subdue it, it must be water cooled.

*sizzle aaaah*

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